The present invention relates generally to integrated circuit memory devices, and more specifically to providing fine granularity power gating of a memory device.
Power gating an integrated circuit memory device generally relates to reducing leakage power in the memory device during operation. A static random access memory (SRAM) is one example of an integrated circuit memory device in which power gating is used to reduce leakage power. A typical SRAM device includes an array of individual SRAM cells each capable of storing a binary voltage value that represents a logical data bit (e.g., “0” or “1”). Power gating an SRAM device generally entails temporarily turning off blocks of cells in the array that are not in use to reduce the overall leakage power of the integrated circuit. During this temporary shutdown of blocks of SRAM cells in the memory array, these blocks operate at a low power mode or a power-gated mode by receiving a reduced voltage supply that is sufficient to retain data. When the blocks of SRAM cells are required for operation they are activated to operate at a full power mode or an active mode by receiving a full voltage supply. These two modes (i.e., active mode and power-gated mode) are switched at an appropriate time and in a suitable manner to maximize power performance while minimizing impact to performance. Power gating blocks of cells in an SRAM device in this manner facilitates the goal of minimizing leakage power by temporarily cutting power off to selective blocks that are not required in the active mode.